NanoIC pilot line technologies
The NanoIC pilot line targets semiconductor technologies that will shape tomorrow’s high-tech solutions. One of the main goals is to develop the process steps and modules that enable these technologies. This will result in stable ‘platformized’ baseline flows with a high technology readiness level (TRL 4-6).
These technologies are situated in three research pillars:
1. Advanced logic technologies
A new generation of logic technologies is needed to fulfill the exploding compute requirements that come, for instance, with further growth of AI. The NanoIC pilot line will develop the processes and modules to enable the integration of:
- the gate-all-around nanosheet beyond the 2nm (N2) technology node
- a complementary field-effect transistor (CFET) baseline flow targeting the A7 logic technology node
In addition, the NanoIC pilot line will further enable high-NA extreme ultraviolet (EUV) lithography.
2. Advanced memory technologies
The success of future AI-driven applications not only depends on the performance of logic technologies. It also hinges on whether these processing units have quick access to (often massive amounts of) data. When it comes to memory, the NanoIC line will further technologies such as:
- spin-orbit torque magneto-resistive random-access memory (SOT-MRAM) architectures
- back end of the line (BEOL)-compatible embedded Dynamic Random Access Memory (eDRAM)
- a 3D memory platform
3. Advanced interconnect technologies
Finally, a crucial way to increase the performance of semiconductor technologies is to remove bottlenecks through next-generation connections that improve, for instance, chiplet integration:
- 3D electrical interconnects for scaled-pitch die-to-wafer (D2W) hybrid bonding and high-density redistribution layer (RDL) technologies
- optical interconnects such as active silicon photonics interposers and GaAs quantum dot (QD) chiplets for D2W hybrid bonding