Advanced PDK workshop: N2 and A14 nanosheet pathfinding and applications
March 25 - 26, 2026 | imec, Leuven, Belgium
Join us for an in-depth workshop on advanced CMOS technology nodes (N2 and A14), co-organized by Europractice and the NanoIC pilot line.
Training information
This two-day event combines theoretical insights with practical design experience, using two different EDA tools: Cadence and Synopsys.
Why join?
- Gain early design experience on the most advanced CMOS technology nodes (N2 and A14), including nanosheet devices, and backside power delivery networks.
- Hands-on exposure: learn practical design flows using Cadence and Synopsys.
- Explore disruptive features such as SRAM memory macros, updated design rules, and system-level integration strategies for beyond-2nm technologies.
- Connect with experts from imec, Europractice, and the NanoIC pilot line to discuss future technology roadmaps and design enablement.
Who should attend?
Design talents from both academia and industry; such as IC designers, researchers, MSc and PhD students, post-docs, professors, and companies preparing for advanced nodes.
Dates
March 25, 9 am - 4 pm (seminars): 100 seats
March 26, 9 am - 4 pm (hands-on workshop): 25 seats
Venue
Imec 1, Kapeldreef 75, Leuven, Belgium
Registration
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