Advanced PDK Workshop: NanoIC’s IGZO‑based eDRAM PDK

Training information

This workshop introduces the key foundations, materials, design principles, and potential applications behind NanoIC’s IGZO‑based eDRAM PDK. Through the day, participants move from exploring the broader memory landscape to understanding the practical implementation of eDRAM architectures with IGZO-based technology, covering oxide‑semiconductor fundamentals, device behaviour, reliability, and design‑technology co‑optimization.

Extra bonus: This event directly precedes NanoIC’s Advanced Interconnect PDK training on May 27th, 2026 (for which practical details will be announced soon). We highly recommend combining both sessions to gain a broader understanding of interconnect technologies right after deep‑diving into IGZO‑based eDRAM.  

Why join this eDRAM workshop?

• Gain a solid understanding of IGZO‑based eDRAM, from device physics to circuit‑level behaviour, to accelerate your learning curve for advanced memory technologies.
• Translate theory into design insights, with practical guidance on how to apply the PDK in exploratory design and simulation flows to evaluate eDRAM architectures.
• Engage with imec experts developing the underlying technology and get answers to your technical questions.
• Prepare for advanced technology nodes, understanding the co‑optimization challenges and opportunities when integrating eDRAM into future chip platforms.
• Get an exclusive guided window tour of imec’s existing 300mm cleanroom.

Agenda (technical presentations)

• Memory landscape, system needs, emerging memories
• Material deposition, morphology, and properties of IGZO
• Transport, material selection rules, and doping for IGZO devices
• Etch development for enabling semiconductor-based eDRAM
• IGZO device fundamentals, optimization, and applications
• IGZO integration and test vehicles for material screening learnings
• Fundamental aspects of IGZO reliability
• DTCO for 2T0C and 3T0C IGZO eDRAM memories
• Sensing schemes for 2T0C IGZO eDRAM
• IGZO eDRAM PDK: what and how

Who should attend? 

Design talents from both academia and industry; such as IC designers, researchers, MSc and PhD students, post-docs, professors, and companies interested in advanced memory solutions.

Attendance fee

100 EUR

Date 

May 26, 9 am – 6 pm  

Venue 

Imec 1, Kapeldreef 75, Leuven, Belgium

Registration

• Participation is open via imec.academy for all external attendees.
• Imec employees can register here through the internal portal.

Registration will close on 11 May 2026, or earlier if all available places are filled.