2025 Symposium on VLSI Technology and Circuits

NanoIC pilot line

Overview of the imec 2025 VLSI papers relevant to the NanoIC pilot line:

• "Extending the Gate-All-Around (GAA) era to the A10 node: Outer Wall Forksheet Enabling Full Channel Strain and Superior Gate Control", L. Verschueren et al. - Technology Session 22: DTCO and Design Enablement
• "Monolithic CFET flow improvements integrating cover spacer and dual-WF RMG" C. Cavalcante et al. - Technology Session 10: Advanced CMOS Platform
• "Shifter materials and stack explorations for Vt fine-tunable dual dipole multi-Vt gate stacks compatible with low thermal budget CFET" H. Arimura et al. - Technology Session 19: Gate Stack and BEOL Transistor Processes
• "SRAM scaling opportunities below 0.01 μm² using double-row CFET architecture with wordline-folded bitcell design for performance optimization" D. Abdi et al. - Technology Session 22: DTCO and Design Enablement
• "Backside power delivery for power switched designs in 2nm CMOS: IR drop and block-level power-performance-area benefits" Y. Zhou et al. - Technology Session 7: 3D Power Delivery Network   
• "Process Insights into 3D-DRAM with vertical bit line and scalable GAA transistor" N. Rassoul et al. - Technology Session 20: DRAM
• "High density, high speed STT-MRAM N7 macros: materials and DTCO exploration" D. Narducci et al. - Technology Session 4: RRAm and MRAM

Event details

The IEEE Symposium on VLSI Technology and Circuits is one of the premiere technical conferences for semiconductor microelectronics, delivering a unique convergence of technology and circuits for the microelectronics industry as a fully merged event to maximize the synergy across both domains.

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